The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to electrically isolate wires from each other and to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.
One difficulty that arises when the dielectric layers are formed from low-k materials is that the reduced strength of the low-k materials, in combination with thinner layers, frequently results in cracking when such materials are subjected to mechanical and thermal stresses. Typical low-k materials in use have included carbon doped silicon dioxide such as commercially available Black Diamond™ and other materials that tend to be porous, thereby reducing the overall dielectric constant. Porous low-k materials have a drawback in that the porosity tends to weaken the overall strength and hardness of the material making crack initiation and propagation more likely. As the requirement for device density increases, the number of levels in an integrated circuit structure has increased to 4 to 10 or more levels. The increased number of material layers contributes to the buildup of compressive and tensile stresses in the multiple layers, especially when subjected to thermal and mechanical stresses, which frequently do not offset one another. The result is that cracking becomes more likely as the number of layers increase and the process wafer is subjected to externally induced stresses that arise when the wafer is cut into the individual dies.
One known approach to alleviate these stresses is to provide crack stop trenches that are located at the die edge to prevent cracking of the die. The crack stop trenches are generally formed simultaneously with the trenches and vias of the metal interconnects. That is, the same lithographic steps used in forming the interconnects, including patterning, etching of the pattern, removal of the mask, and etching, are generally used to form the crack stop trenches. One problem with this approach is that the lithographic steps used to form the metal interconnects are optimized to form lithographic features (e.g., trench and via widths) with relatively small dimensions suitable for higher device densities. Unfortunately, the width of the crack stop trenches are preferably one or more orders of magnitude greater than the width of the trenches used for the metal interconnects. This limitation can be mitigated to some extent by providing two or more crack stop trenches in parallel with one another. Moreover, since the crack stop trenches are formed at the same time as the metal interconnects, the conductive material (e.g., copper) filling both types of trenches is generally the same. While this material is typically chosen to have a suitably low dielectric constant, it generally will not also provide the optimal immunity to cracking that is desired. Accordingly, the formation of the interconnect trenches and vias and the crack stop trenches in the same process steps is often problematic.